专利图示简要描述撰写

Brief Description of the Drawings

• Figure 1 is a perspective view of an exemplary wearable electrocardiogram (ECG) acquisition apparatus 100 configured for thoracic placement, depicting a housing 110, an adjustable attachment band 120, and a distributed electrode array 130 including a reference/common-mode electrode 136.

• Figure 2 is an exploded view of the apparatus 100 showing, in order, an exterior housing 110, a compliant substrate 112, a flexible printed circuit assembly 114, an electromagnetic shield 116, a rechargeable battery 170, a gasket 118, and the electrode array 130 disposed on a skin-facing surface.

• Figure 3 is a functional block diagram of the electronics, illustrating an analog front end (AFE) 140 coupled to the electrode array 130 through a reconfigurable switch matrix 131, an impedance/contact-quality module 138 for electrode self-calibration, a noise suppression module 152 comprising both common-mode rejection and digital artifact mitigation, a microcontroller or system-on-chip 148, a timing and synchronization subsystem 162 disciplined by a local oscillator 166, and a wireless transceiver 160.

• Figure 4 is a plan view of the self-calibrating electrode layout 130, identifying a plurality of sensing electrodes E1–E6, a dedicated reference/common-mode electrode 136, optional auxiliary calibration electrodes Ec, interelectrode spacing parameters s1–sN, and conductive traces to the switch matrix 131 enabling dynamic selection of operative leads.

• Figure 5 is a flowchart of a calibration routine 300 executed by controller 148: (i) measure skin–electrode impedance and contact pressure for each electrode; (ii) compute signal-to-noise and motion sensitivity indices; (iii) select a lead configuration and designate the common-mode return; (iv) program AFE gain and DRL parameters; (v) store mapping to non-volatile memory; and (vi) perform periodic or event-triggered re-evaluation.

• Figure 6 is a partial schematic of the AFE 140 and noise suppression paths, including an instrumentation amplifier 142 with programmable gain, a driven common-mode (DRL) circuit 144 operably coupled to electrode 136, an anti-aliasing filter, an analog-to-digital converter 146 with sample clocking at the conversion edge, and a digital signal processing chain comprising an adaptive notch filter 154, baseline wander correction 156, and motion-artifact cancellation using inertial data from a motion sensor 150.

• Figure 7 is a timing diagram of wireless synchronization, showing reception of a timing beacon by transceiver 160, estimation of propagation and processing delay, update of a disciplined clock 166 within module 162, and time-stamped ECG sample emission with residual drift compensation and jitter bounding.

• Figure 8 is a system-level diagram illustrating concurrent synchronization of multiple apparatuses 100 with a base station 200, which is in turn referenced to a network time source 202; device-side clock discipline within module 162 and inter-device alignment are indicated.

• Figure 9 is a cross-sectional view through a representative electrode assembly, showing a conductive cap 132 or hydrogel interface 134, a compliant carrier 112, a via to shielded routing, a guard/ground ring for fringe-field control, and a patient-isolation barrier configured to meet applicable medical safety insulation requirements.

• Figure 10 is an environmental view highlighting electromagnetic compatibility features, including shield 116, controlled-impedance traces, and common-mode chokes at the antenna feed, configured to mitigate external radio-frequency interference during concurrent wireless operation.

Reference Numerals

• 100: wearable ECG acquisition apparatus
• 110: housing
• 112: compliant substrate
• 114: flexible printed circuit assembly
• 116: electromagnetic shield
• 118: gasket
• 120: attachment band/strap
• 130: electrode array
• 131: reconfigurable switch matrix
• 132: dry sensing electrode
• 134: hydrogel sensing electrode (optional)
• 136: reference/common-mode (DRL) electrode
• 138: impedance/contact-quality module
• 140: analog front end (AFE)
• 142: instrumentation amplifier
• 144: driven common-mode (DRL) circuit
• 146: analog-to-digital converter (ADC)
• 148: microcontroller/system-on-chip (SoC)
• 150: motion sensor (e.g., IMU)
• 152: noise suppression module
• 154: adaptive notch filter
• 156: baseline wander correction
• 158: artifact rejection logic
• 160: wireless transceiver
• 162: time synchronization module
• 166: local oscillator/clock (e.g., TCXO)
• 168: power management
• 170: rechargeable battery
• 172: charging interface
• 174: contact pressure sensor(s)
• 176: temperature sensor
• 180: non-volatile memory
• 182: firmware storage
• 200: base station/gateway
• 202: network time reference

Drawing Conventions

• Like reference numerals refer to like elements throughout the drawings.
• The drawings are not to scale and are schematic in certain respects; relative sizes and positions may be adjusted for clarity.
• Functional blocks represent hardware, software, firmware, or combinations thereof configured to perform the stated functions; claim scope is not limited to the depicted partitioning.

附图简要说明 为便于对本发明低功耗边缘AI相机之结构与方法进行清晰、完整的理解，现结合附图对各实施例予以简要说明。所示附图用于说明而非限定本发明的保护范围；在不背离本发明实质的前提下，元件形状、比例及相互位置可作工程性变更。

图1为本发明低功耗边缘AI相机的外观示意图，示出具有可更换镜头座的紧凑型机身布局。

图2为图1所示相机的爆炸示意图，示出可更换镜头座、卡口锁定机构、法兰距调整组件及与图像传感器的相对定位关系。

图3为本发明相机的系统功能框图，示出图像传感器、ISP、处理器/AI加速器、双缓冲存储结构、DMA控制、非易失存储、电源管理、时钟与安全模块等功能单元及其信号关联。

图4为本发明双缓冲推理管线的流程框图，示出帧采集、预处理、缓冲区写入、并行推理、后处理与结果输出的流水式作业，以及缓冲区在连续帧间的交替机制。

图5为双缓冲推理的时序示意图，说明在帧n与帧n−1间，采集/写入与推理/读取的并行关系、缓冲区交换时点及DMA与AI加速器的资源占用错峰。

图6为离线检测工作状态机图，示出低功耗监测、触发唤醒、采集推理、结果决策、结果存储与回到休眠的闭环逻辑，以及在网络不可用场景下的本地缓存与延迟上报。

图7为低功耗电源域及能耗控制示意图，示出多电源域划分、电源门控、动态电压频率调整（DVFS）、时钟门控与各唤醒源的耦合关系。

图8为可更换镜头座的结构剖视图，示出卡口/螺纹接口、法兰距补偿组件、镜头识别触点（如设置）、防尘/防水密封及与散热结构的装配关系。

图9为镜头识别与标定的流程示意图，示出镜头ID读取、畸变/内参加载、ISP参数切换与推理前预处理参数自适应。

图10为边缘模型的安全存储与离线更新框图，示出模型分区、完整性校验、安全启动链路、离线包更新与故障回退机制。

图11为本地结果缓存与环形队列示意图，示出检测结果与必要片段在本地加密存储、容量管理及联机后的批量同步策略。

图12为本发明相机在典型部署场景中的安装示意图（可选实施例），示出室内/室外安装方式、遮光与防护结构的相对关系。

附图标记说明 100 相机总体 110 外壳 120 可更换镜头座 121 卡口锁定机构 122 适配环 123 法兰距调整垫片 124 密封圈 130 镜头组件 140 图像传感器 150 ISP模块 160 AI加速器/NPU 170 处理器/SoC/MCU 180 易失性存储器 181 缓冲区A 182 缓冲区B 190 非易失性存储器 200 电源管理模块 210 时钟/RTC 220 触发传感器（如PIR/光敏/定时器） 230 接口模块（可选） 240 安全单元/硬件信任根 250 本地结果缓存/存储 260 通信模块（可选） 270 散热组件 280 防护构件 310 DMA控制器 320 帧同步控制器 330 DVFS控制器 400 状态机模块 410 预处理模块 420 推理模块 430 后处理模块 440 事件管理模块

说明

• 上述附图着重展示本发明在低功耗约束下，通过双缓冲推理管线实现连续帧不丢失的边缘推理能力，并通过可更换镜头座实现成像系统的可配置性，以适配不同焦距与应用场景。离线检测通过本地模型与结果缓存实现对网络依赖的解除。
• 附图所示模块可为软硬件实现的功能单元，其边界可依据具体实现进行拆分或合并，均不影响本发明的实质。