Brief Description of the Drawings
- Figure 1 is a perspective view of an exemplary wearable electrocardiogram (ECG) acquisition apparatus 100 configured for thoracic placement, depicting a housing 110, an adjustable attachment band 120, and a distributed electrode array 130 including a reference/common-mode electrode 136.
- Figure 2 is an exploded view of the apparatus 100 showing, in order, an exterior housing 110, a compliant substrate 112, a flexible printed circuit assembly 114, an electromagnetic shield 116, a rechargeable battery 170, a gasket 118, and the electrode array 130 disposed on a skin-facing surface.
- Figure 3 is a functional block diagram of the electronics, illustrating an analog front end (AFE) 140 coupled to the electrode array 130 through a reconfigurable switch matrix 131, an impedance/contact-quality module 138 for electrode self-calibration, a noise suppression module 152 comprising both common-mode rejection and digital artifact mitigation, a microcontroller or system-on-chip 148, a timing and synchronization subsystem 162 disciplined by a local oscillator 166, and a wireless transceiver 160.
- Figure 4 is a plan view of the self-calibrating electrode layout 130, identifying a plurality of sensing electrodes E1–E6, a dedicated reference/common-mode electrode 136, optional auxiliary calibration electrodes Ec, interelectrode spacing parameters s1–sN, and conductive traces to the switch matrix 131 enabling dynamic selection of operative leads.
- Figure 5 is a flowchart of a calibration routine 300 executed by controller 148: (i) measure skin–electrode impedance and contact pressure for each electrode; (ii) compute signal-to-noise and motion sensitivity indices; (iii) select a lead configuration and designate the common-mode return; (iv) program AFE gain and DRL parameters; (v) store mapping to non-volatile memory; and (vi) perform periodic or event-triggered re-evaluation.
- Figure 6 is a partial schematic of the AFE 140 and noise suppression paths, including an instrumentation amplifier 142 with programmable gain, a driven common-mode (DRL) circuit 144 operably coupled to electrode 136, an anti-aliasing filter, an analog-to-digital converter 146 with sample clocking at the conversion edge, and a digital signal processing chain comprising an adaptive notch filter 154, baseline wander correction 156, and motion-artifact cancellation using inertial data from a motion sensor 150.
- Figure 7 is a timing diagram of wireless synchronization, showing reception of a timing beacon by transceiver 160, estimation of propagation and processing delay, update of a disciplined clock 166 within module 162, and time-stamped ECG sample emission with residual drift compensation and jitter bounding.
- Figure 8 is a system-level diagram illustrating concurrent synchronization of multiple apparatuses 100 with a base station 200, which is in turn referenced to a network time source 202; device-side clock discipline within module 162 and inter-device alignment are indicated.
- Figure 9 is a cross-sectional view through a representative electrode assembly, showing a conductive cap 132 or hydrogel interface 134, a compliant carrier 112, a via to shielded routing, a guard/ground ring for fringe-field control, and a patient-isolation barrier configured to meet applicable medical safety insulation requirements.
- Figure 10 is an environmental view highlighting electromagnetic compatibility features, including shield 116, controlled-impedance traces, and common-mode chokes at the antenna feed, configured to mitigate external radio-frequency interference during concurrent wireless operation.
Reference Numerals
- 100: wearable ECG acquisition apparatus
- 110: housing
- 112: compliant substrate
- 114: flexible printed circuit assembly
- 116: electromagnetic shield
- 118: gasket
- 120: attachment band/strap
- 130: electrode array
- 131: reconfigurable switch matrix
- 132: dry sensing electrode
- 134: hydrogel sensing electrode (optional)
- 136: reference/common-mode (DRL) electrode
- 138: impedance/contact-quality module
- 140: analog front end (AFE)
- 142: instrumentation amplifier
- 144: driven common-mode (DRL) circuit
- 146: analog-to-digital converter (ADC)
- 148: microcontroller/system-on-chip (SoC)
- 150: motion sensor (e.g., IMU)
- 152: noise suppression module
- 154: adaptive notch filter
- 156: baseline wander correction
- 158: artifact rejection logic
- 160: wireless transceiver
- 162: time synchronization module
- 166: local oscillator/clock (e.g., TCXO)
- 168: power management
- 170: rechargeable battery
- 172: charging interface
- 174: contact pressure sensor(s)
- 176: temperature sensor
- 180: non-volatile memory
- 182: firmware storage
- 200: base station/gateway
- 202: network time reference
Drawing Conventions
- Like reference numerals refer to like elements throughout the drawings.
- The drawings are not to scale and are schematic in certain respects; relative sizes and positions may be adjusted for clarity.
- Functional blocks represent hardware, software, firmware, or combinations thereof configured to perform the stated functions; claim scope is not limited to the depicted partitioning.
